/*
utf-8
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电平转边沿触发信号输出程序
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由刘丙旭出品
遵循署名-非商业性使用-相同方式共享 4.0 国际协议 (CC BY-NC-SA 4.0)
详情访问https://creativecommons.org/licenses/by-nc-sa/4.0/deed.zh
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*/
module FF(clk,rst,in,out_posedge,out_negedge,out_pos_neg);
	input in,clk,rst;
	output out_posedge,out_negedge,out_pos_neg;
	
	reg out_posedge,out_negedge;
	reg out_tem;
	
	always @(posedge clk or posedge rst)
	if(rst == 1'b1)
	begin
		out_tem <= 1'b0;
		out_posedge <= 1'b0;
		out_negedge <= 1'b0;
	end
	
	else
	begin
		out_tem <= in;
		out_negedge <= out_tem & ~in;
		out_posedge <= ~out_tem & in;
	end
	
	assign out_pos_neg = out_negedge | out_posedge;
	
endmodule